In recent advancement of digital technologies in electronic hardware, larger-capacity and nonvolatile semiconductor memory apparatuses have been vigorously developed in order to store data of music, images, information and so on. For example, nonvolatile semiconductor memory apparatuses using ferroelectric substances as capacitive elements are now used in various fields. Furthermore, in contrast to the nonvolatile memory apparatus using the ferroelectric capacitors, a nonvolatile semiconductor memory apparatus (hereinafter referred to as ReRAM) using a material whose resistance value changes according to electric pulses applied and continues to keep its state has attracted an attention because it can easily have compatibility with a normal semiconductor process.
For example, there is disclosed an apparatus configuration, for enabling the use of the existing DRAM step as it is, in a ReRAM including one transistor and one memory portion (see, e.g., patent document 1). The ReRAM includes transistors and nonvolatile memory portions connected to drains of the transistors. The memory portion has a structure in which a resistance variable layer whose resistance reversibly changes according to current pulses applied is sandwiched between an upper electrode and a lower electrode. As the resistance variable layer, a nickel oxide (NiO), a vanadium oxide (V2O5), a zinc oxide (ZnO), a niobium oxide (Nb2O5), a titanium oxide (TiO2), a tungsten oxide (WO3), a cobalt oxide (CoO), etc is used. It is known that the transition metal oxide is allowed to have a specified resistance value by application of a voltage or current having a threshold or higher and to hold the resistance value until the transition metal oxide is newly applied with a voltage or current. And, the transition metal oxide can be manufactured using the existing DRAM step as it is.
The above illustrated example includes one transistor and one nonvolatile memory portion. Also, a cross-point ReRAM using a perovskite structure material is also disclosed (see, e.g., patent document 2). This ReRAM has a structure in which stripe-shaped lower electrodes are provided on a substrate and an active layer is provided so as to cover the entire surface of the lower electrodes. As the active layer, a resistance variable layer whose resistance reversibly changes according to electric pulses is used. On the active layer, stripe-shaped upper electrodes are provided to respectively cross the lower electrodes at a right angle. A region where each of the lower electrodes and each of the upper electrodes cross each other such that the active layer is sandwiched between the lower electrode and the upper electrode forms a memory portion. The lower electrodes and the upper electrodes serve as word lines or bit lines. With such a cross-point configuration, a larger capacity is attainable.
In the cross-point ReRAM, a diode is incorporated into the ReRAM such that the diode is connected in series with the resistance variable layer to avoid the influence from the resistance variable layers on another rows or columns, when reading the resistance value of the resistance variable layer provided at the cross-point.
For example, a ReRAM is disclosed, which comprises a substrate including two or more bit lines arranged to extend at parallel intervals, two or more word lines arranged to extend at parallel intervals and to cross the bit lines, resistor structures provided at points where the bit lines and the word lines cross each other and are located on the bit lines, and diode structures provided on the resistor structures in contact with the resistor structures and the word lines, lower electrodes provided on the substrate, resistor structures provided on the lower electrodes, diode structures provided on the resistor structures, and upper electrodes provided on the diode structures (see, e.g., patent document 3).
In such a configuration, since a unit cell structure is allowed to have a laminated-layer structure in which one diode structure and one resistor structure are continuously laminated, an array cell structure is easily attainable.
A ReRAM having a cross-point configuration is also disclosed, in which memory plugs are arranged at cross points where X-direction conductive array lines and Y-direction conductive array lines cross each other (e.g., see patent document 4). The memory plug is formed by seven layers. A composite metal oxide sandwiched between two electrode layers forms a memory element. A metal-insulator-metal (MIM) structure provided on the memory element forms a non-ohmic device.
The cross-point configuration is used for MRAM, or the like. Various studies have been made to solve the similar problems. For example, a laminated structure in which word lines, resistance variable layer patterns, semiconductor layer patterns and bit lines are laminated, is disclosed, in which the resistance variable layer pattern and the semiconductor layer pattern form a schottky diode, or the semiconductor layer pattern and the bit line form a schottky diode (see patent document 5).
Or, a MRAM including a plurality of word lines, a plurality of bit lines, and resistive intersection array of memory cells is disclosed, in which the memory cells are connected to bit lines and separate diodes and the separate diodes are connected to respective word lines (see e.g., patent document 6). The separate diode is formed as a schottky-metal-semiconductor diode, and its metal portion is suitably made of platinum (Pt).    Patent document 1: Japanese Laid-Open Patent Application Publication No. 2004-363604    Patent Document 2: Japanese Laid-Open Patent Application Publication No. 2003-68984    Patent document 3: Japanese Laid-Open Patent Application Publication No. 2006-140489    Patent document 4: U.S. Pat. No. 6,753,561 specification    Patent document 5: Japanese Laid-Open Patent Application Publication No. 2003-197880    Patent Document 6: Japanese Laid-Open Patent Application Publication No. 2003-273335